MC68000

Intel 8086から遅れて2年、 1980年、Motorola社から発表。
使用トランジスタ数 約68,000個 3.5μm HMOS(発表時)
32bitデーターレジスタ8個
32bitアドレスレジスタ8個
4,6,8,10,12.5,16,20MHz
外部アドレスバス 24bit
外部データバス 16bit
ビッグ・エンディアン
割込みベクターは0～1023番地の固定
スーパバイザとユーザモードをもつ
スーパバイザとユーザモードそれぞれ専用のSPをもつ。
64ピンDIP
ページフォールトの際に実行中だった命令の実行からの再開ができないので仮想記憶をサポートしていない。

MC68008

1982年、Motorola社から発表。
MC68000の8bitデーターバス版
外部アドレスバス 20bit
48ピンDIP
52-QUAD PACKAGE

MC68010

1982年、Motorola社から発表。
ユーザーモードはMC68000の上位互換
仮想記憶対応。
外部アドレスバス 24bit
割り込みベクターテーブルのアドレスを変更可能(VBR)
メモリアクセス時のファンクションコードを変更可能なレジスタと特権命令を追加
SFC,DFC
MOVES
MOVEC
RTD
64ピンDIP
68-QUAD PACKAGE
68-GRID ARRAY

MC68020

1984年、Motorola社から発表。
完全32bit化
MC68010の上位互換
256byte命令キャッシュ(64line line size 4byte ダイレクトマップ)
2μmのHCMOSプロセスで約200000トランジスタ
メモリアクセス時にデーターバス幅を8bit,16bitに変更可能なダイナミックバスサイジングを搭載。
ビッグ・エンディアンなので8bit時はD31～D24、16bit時はD31～D16に接続します。
スーパバイザスタックポインタがISPとMSPに分離。
スケールドインデックスをサポート
ポインターのポインターであるメモリー間接モードの追加
ビットフィールド命令の追加

MC68030

1987年、Motorola社から発表。
MC68020の上位互換
256byte命令キャッシュ 16line line size 16byte ダイレクトマップ
256byteデータキャッシュ 16line line size 16byte ダイレクトマップ
約30万トランジスタ
MC68851サブセット相当のデマンドページ方式仮想記憶対応MMU搭載
アドレス変換キャッシュは22エントリ
バースト転送サポート

MC68040

1990年、Motorola社から発表
MC68030の上位互換
120万トランジスタ
6段パイプライン
命令キャッシュ 4k 64set 16 byte line size 4way
データキャッシュ 4k 64set 16 byte line size 4way
FPU内臓(MC68882相当) 超越関数はソフトウェアエミュレーション

MC68060

1994年、Motorola社から発表。
MC68040の上位互換
250万トランジスタ
デュアルパイプライン
4k,8k page
命令キャッシュ 8k 128set 16 byte line size 4way
データキャッシュ 8k 128set 16 byte line size 4way
アドレス変換キャッシュは64エントリ(4way)

MC68851(PMMU)

MC68020用のページング方式のMMUである。
ページサイズは256,512,1k,2k,4k,8k,16k,32kbyteを指定可能。
フルアソシアティブ方式の64エントリ変換キャッシュ搭載。
変換は3レベル
コプロセッサ形式

MC68881/MC68882(FPU)

浮動小数点コプロセッサ
8個のレジスタ
拡張倍精度浮動小数点、倍精度浮動小数点、単精度浮動小数点をサポート
8bit、16bit、32bit整数をサポート
10進形式の浮動小数点をサポート(仮数16桁、指数3桁)
超越関数をサポート

m68k

レジスタ(User Programming Model)

32bitデーターレジスタが8本
32bitアドレスレジスタが8本
FPn、FPCR、FPSR、FPIARレジスタはMC68040以降およびMC68020/MC6030にFPU(MC68881/MC68882)を接続した時に使用可能。
Data Regsiters
31150
D0
D1
D2
D3
D4
D5
D6
D7
Address Regsiters
31150
A0
A1
A2
A3
A4
A5
A6
USP
31150
PC
CCR
790
FP0
FP1
FP2
FP3
FP4
FP5
FP6
FP7
310
FPCR
FPSR
FPIAR

CCR(User Byte)

76543210
000XNZVC
Xフラグ
精度拡張用
Nフラグ
負
Zフラグ
ゼロ
Vフラグ
桁あふれ
Cフラグ
桁上げ

命令

凡例

MPU
0:MC68000/MC68008
1:MC68010
2:MC68020
3:MC68030
4:MC68040
6:MC68060
M:MC68851(MC68020)
C:MC68881/MC68882(MC68020/MC68030)
S:ソフトウェアエミュレーション(MC68040/MC68060)
-:未サポート

一覧

68xxx
instop MPUFEDCBA98 76543210 FEDCBA98 76543210 FEDCBA98 76543210
ABCD.B -(As),-(Ad)-(As)+ -(Ad)+X→(Ad) BCD0123461 1 0 0dreg1 0 0 0 0 1sreg
ABCD.B Ds,DdDs+Dd+X→Dd BCD0123461 1 0 0dreg1 0 0 0 0 0sreg
ADD.sz <ea>,Dd<ea>+Dd→Dd0123461 1 0 1dreg 0szsmodsreg
ADD.W <ea>,Ad<ea>+Ad→Ad0123461 1 0 1dreg0 1 1smodsreg
ADD.sz Ds,<ea>Ds+<ea>→<ea>0123461 1 0 1sreg 1szdmoddreg
ADD.L <ea>,Ad<ea>+Ad→Ad0123461 1 0 1dreg1 1 1smodsreg
ADDI.sz #<data>,<ea>#<data>+<ea>→<ea>0123460 0 0 0 0 1 1 0 0 0dmoddreg
ADDQ.sz #<data>,<ea>#<data>+<ea>→<ea>0123460 1 0 1data 0szdmoddreg
ADDX.sz -(As),-(Ad)-(As)+ -(Ad)+X→(Ad)0123461 1 0 1dreg 1sz0 0 1sreg
ADDX.sz Ds,DdDs+Dd→Dd0123461 1 0 1dreg 1sz0 0 0sreg
ALINE #<data>0123461 0 1 0d
AND.sz #<data>,<ea>#<data>∧<ea>→<ea>0123460 0 0 0 0 0 1 0szdmoddreg
AND.sz <ea>,Dd<ea>∧Dd→Dd0123461 1 0 0dreg 0szsmodsreg
AND.sz Ds,<ea>Ds∧<ea>→<ea>0123461 1 0 0sreg 1szdmoddreg
ANDI.B #<data>,CCR#<data>∧CCR→CCR0123460 0 0 0 0 0 1 0 0 0 1 1 1 1 0 0
ANDI.W #<data>,SR#<data>∧SR→SR0123460 0 0 0 0 0 1 0 0 1 1 1 1 1 0 0
ASL.W <ea>算術左シフト0123461 1 1 0 0 0 0 1 1 1dmoddreg
ASL.sz Dd0123461 1 1 0 0 0 1 1sz0 0 0dreg
ASL.sz #<data>,Dd0123461 1 1 0data1 0 0 0 0 0dreg
ASL.sz Ds,Dd0123461 1 1 0sreg1 0sz0 0dreg
ASR.sz #<data>,Dd算術右シフト0123461 1 1 0data 0sz0 0 0dreg
ASR.sz Dw,Dr0123461 1 1 0sreg0 0sz0 0dreg
ASR.sz Dd0123461 1 1 0 0 0 1 0sz0 0 0dreg
ASR.W <ea>0123461 1 1 0 0 0 0 0 1 1dmoddreg
BCC.L <label>if cc then PC+d→PC--23460 1 1 0cc1 1 1 1 1 1 1 1
BCC.W <label>if cc then PC+d→PC0123460 1 1 0cc0 0 0 0 0 0 0 0
BCC.S <label>if cc then PC+d→PC0123460 1 1 0ccdata
BCHG.B Ds,<ea>~ (<Bit Number> of Destination) →Bit of Destination0123460 0 0 0sreg1 0 1dmoddreg
BCHG.B #<data>,<ea>~ (<Bit Number> of Destination) →Bit of Destination0123460 0 0 0 1 0 0 0 0 1dmoddreg
BCHG.L Ds,Dd~ (<Bit Number> of Destination) →Bit of Destination0123460 0 0 0sreg1 0 1 0 0 0dreg
BCLR.B #<data>,<ea>0→Bit of Destination0123460 0 0 0 1 0 0 0 1 0dmoddreg
BCLR.B Ds,<ea>0→Bit of Destination0123460 0 0 0sreg1 1 0dmoddreg
BCLR.L #<data>,Dd0→Bit of Destination0123460 0 0 0 1 0 0 0 1 0 0 0 0dreg
BCLR.L Ds,Ds0→Bit of Destination0123460 0 0 0sreg1 1 0 0 0 0dreg
BFCHG <ea>{#o:#w}~Field→Field--23461 1 1 0 1 0 1 0 1 1dmoddreg0 0 0 0 0o 0w
BFCHG <ea>{#o:Dw}~Field→Field--23461 1 1 0 1 0 1 0 1 1dmoddreg0 0 0 0 0o1 0 0w
BFCHG <ea>{Do:#w}~Field→Field--23461 1 1 0 1 0 1 0 1 1dmoddreg0 0 0 0 1 0 0o 0w
BFCHG <ea>{Do:Dw}~Field→Field--23461 1 1 0 1 0 1 0 1 1dmoddreg0 0 0 0 1 0 0o1 0 0w
BFCLR <ea>{#o:#w}0→Field--23461 1 1 0 1 1 0 0 1 1dmoddreg0 0 0 0 0o 0w
BFCLR <ea>{#o:Dw}0→Field--23461 1 1 0 1 1 0 0 1 1dmoddreg0 0 0 0 0o1 0 0w
BFCLR <ea>{Do:#w}0→Field--23461 1 1 0 1 1 0 0 1 1dmoddreg0 0 0 0 1 0 0o 0w
BFCLR <ea>{Do:Dw}0→Field--23461 1 1 0 1 1 0 0 1 1dmoddreg0 0 0 0 1 0 0o1 0 0w
BFEXTS <ea>{#o:#w},DdField→Dn; Sign-Extended--23461 1 1 0 1 0 1 1 1 1smodsreg0dreg 0o 0w
BFEXTS <ea>{#o:Dw},DdField→Dn; Sign-Extended--23461 1 1 0 1 0 1 1 1 1smodsreg0dreg 0o1 0 0w
BFEXTS <ea>{Do:#w},DdField→Dn; Sign-Extended--23461 1 1 0 1 0 1 1 1 1smodsreg0dreg1 0 0o 0w
BFEXTS <ea>{Do:Dw},DdField→Dn; Sign-Extended--23461 1 1 0 1 0 1 1 1 1smodsreg0dreg1 0 0o1 0 0w
BFEXTU <ea>{#o:#w},DdField→Dn; Zero-Extended--23461 1 1 0 1 0 0 1 1 1smodsreg0dreg 0o 0w
BFEXTU <ea>{#o:Dw},DdField→Dn; Zero-Extended--23461 1 1 0 1 0 0 1 1 1smodsreg0dreg 0o1 0 0w
BFEXTU <ea>{Do:#w},DdField→Dn; Zero-Extended--23461 1 1 0 1 0 0 1 1 1smodsreg0dreg1 0 0o 0w
BFEXTU <ea>{Do:Dw},DdField→Dn; Zero-Extended--23461 1 1 0 1 0 0 1 1 1smodsreg0dreg1 0 0o1 0 0w
BFFFO <ea>{#o:#w},DdScan for First Bit Set in Field; Offset→Dn--23461 1 1 0 1 1 0 1 1 1smodsreg0dreg 0o 0w
BFFFO <ea>{#o:Dw},DdScan for First Bit Set in Field; Offset→Dn--23461 1 1 0 1 1 0 1 1 1smodsreg0dreg 0o1 0 0w
BFFFO <ea>{Do:#w},DdScan for First Bit Set in Field; Offset→Dn--23461 1 1 0 1 1 0 1 1 1smodsreg0dreg1 0 0o 0w
BFFFO <ea>{Do:Dw},DdScan for First Bit Set in Field; Offset→Dn--23461 1 1 0 1 1 0 1 1 1smodsreg0dreg1 0 0o1 0 0w
BFINS Dn,<ea>{#o:#w}Dn→Field--23461 1 1 0 1 1 1 1 1 1dmoddreg0sreg 0o 0w
BFINS Dn,<ea>{#o:Dw}Dn→Field--23461 1 1 0 1 1 1 1 1 1dmoddreg0sreg 0o1 0 0w
BFINS Dn,<ea>{Do:#w}Dn→Field--23461 1 1 0 1 1 1 1 1 1dmoddreg0sreg1 0 0o 0w
BFINS Dn,<ea>{Do:Dw}Dn→Field--23461 1 1 0 1 1 1 1 1 1dmoddreg0sreg1 0 0o1 0 0w
BFSET <ea>{#o:#w}1→Field--23461 1 1 0 1 1 1 0 1 1dmoddreg0 0 0 0 0o 0w
BFSET <ea>{#o:Dw}1→Field--23461 1 1 0 1 1 1 0 1 1dmoddreg0 0 0 0 0o1 0 0w
BFSET <ea>{Do:#w}1→Field--23461 1 1 0 1 1 1 0 1 1dmoddreg0 0 0 0 1 0 0o 0w
BFSET <ea>{Do:Dw}1→Field--23461 1 1 0 1 1 1 0 1 1dmoddreg0 0 0 0 1 0 0o1 0 0w
BFTST <ea>{#o:#w}1→Field--23461 1 1 0 1 0 0 0 1 1smodsreg0 0 0 0 0o 0w
BFTST <ea>{#o:Dw}1→Field--23461 1 1 0 1 0 0 0 1 1smodsreg0 0 0 0 0o1 0 0w
BFTST <ea>{Do:#w}1→Field--23461 1 1 0 1 0 0 0 1 1smodsreg0 0 0 0 1 0 0o 0w
BFTST <ea>{Do:Dw}1→Field--23461 1 1 0 1 0 0 0 1 1smodsreg0 0 0 0 1 0 0o1 0 0w
BKPT #<data>-123460 1 0 0 1 0 0 0 0 1 0 0 1data
BSET.B #<data>,<ea>1→Bit of Destination0123460 0 0 0 1 0 0 0 1 1dmoddreg
BSET.B Ds,<ea>1→Bit of Destination0123460 0 0 0sreg1 1 1dmoddreg
BSET.L #<data>,Dd1→Bit of Destination0123460 0 0 0 1 0 0 0 1 1 0 0 0dreg
BSET.L Ds,Dd1→Bit of Destination0123460 0 0 0sreg1 1 1 0 0 0dreg
BSR.L <label>--23460 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1
BSR.S <label>0123460 1 1 0 0 0 0 1data
BSR.W <label>0123460 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0
BTST.B #<data>,<ea>~ (<Bit Number> of Destination)→Z0123460 0 0 0 1 0 0 0 0 0dmoddreg
BTST.B Ds,<ea>~ (<Bit Number> of Destination)→Z0123460 0 0 0sreg1 0 0dmoddreg
BTST.L #<data>,Dr~ (<Bit Number> of Destination)→Z0123460 0 0 0 1 0 0 0 0 0 0 0 0dreg
BTST.L Ds,Dr~ (<Bit Number> of Destination)→Z0123460 0 0 0sreg1 0 0 0 0 0dreg
CALLM #<data>,<ea>--2---0 0 0 0 0 1 1 0 1 1dmoddreg0 0 0 0 0 0 0 0data
CAS.sZ Dc,Du,<ea><ea>==Dc ? Du→<ea> : <ea>→Dc--23460 0 0 0 1sz0 1 1dmoddreg0 0 0 0 0 0 0ureg0 0 0creg
CAS2.sZ Dc1:Dc2,Du1:Du2,(Rn1):(Rn2)Rn1==Dc1 && Rn2==Dc2 ? Du1→Rn1,Du2→Rn2 : Rn1→Dc1,Rn2→Dc2--234S0 0 0 0 1sz0 1 1 1 1 1 1 0 0dan1reg0 0 0u1reg0 0 0c1regdan2reg0 0 0u2reg0 0 0c2reg
CHK.L <ea>,Ddif Dn<0 || <ea><Dn then Trap--23460 1 0 0dreg1 0 0smodsreg
CHK.W <ea>,Ddif Dn<0 || <ea><Dn then Trap0123460 1 0 0dreg1 1 0smodsreg
CHK2.sz <ea>,Rdif Rd<LB || UB<Rd then Trap--234S0 0 0 0 0sz0 1 1smodsregdadreg1 0 0 0 0 0 0 0 0 0 0 0
CINVA cacheInvalidate Selected Cache Lines----461 1 1 1 0 1 0 0cache0 1 1 0 0 0
CINVc cache,(As)Invalidate Selected Cache Lines----461 1 1 1 0 1 0 0cache 0scopesreg
CLR.sz <ea>0→<ea>0123460 1 0 0 0 0 1 0szdmoddreg
CLR.L Ad0→Ad0123461 0 0 1dreg1 1 1 0 0 1dreg
CLR.W Ad0→Ad0123461 0 0 1dreg0 1 1 0 0 1dreg
CMP.W <ea>,AdAd-<ea>0123461 0 1 1dreg0 1 1smodsreg
CMP.L <ea>,AdAd-<ea>0123461 0 1 1dreg1 1 1smodsreg
CMP.sz <ea>,DdDd-<ea>0123461 0 1 1dreg 0szsmodsreg
CMP.sz #<data>,<ea><ea>-#<data>01----0 0 0 0 1 1 0 0szdmoddreg
CMP2.sz <ea>,RdRn<LB || UB<Rn--234S0 0 0 0 0sz0 1 1smodsregdadreg0 0 0 0 0 0 0 0 0 0 0 0
CMPM.B (As)+,(Ad)+(Ad)+ - (As)+0123461 0 1 1sreg 1sz0 0 1dreg
CPUSHc cachePush and Invalidate Cache Lines----461 1 1 1 0 1 0 0cache 1scope0 0 0
CPUSHc cache,(As)Push and Invalidate Cache Lines----461 1 1 1 0 1 0 0cache 1scopesreg
DBCC.W Dd,<label>if !cc then Dn-1→Dn,if Dn≠-1 then PC+d→PC0 1 0 1cc1 1 0 0 1dreg
DIVS.L <ea>,DdDd÷<ea>→Dd--23460 1 0 0 1 1 0 0 0 1smodsreg0dreg1 0 0 0 0 0 0 0 0dreg
DIVS.L <ea>,Dh:DlDh:Dl÷<ea>→Dh,Dl--234S0 1 0 0 1 1 0 0 0 1smodsreg0dlreg1 1 0 0 0 0 0 0 0dheg
DIVS.W <ea>,DdDd÷<ea>→Dd0123461 0 0 0dreg1 1 1smodsreg
DIVSL.L <ea>,Dh:DlDh:Dl÷<ea>→Dh,Dl--23460 1 0 0 1 1 0 0 0 1smodsreg0dhreg1 0 0 0 0 0 0 0 0dlreg
DIVU.L <ea>,DdDd÷<ea>→Dd--23460 1 0 0 1 1 0 0 0 1smodsreg0dreg0 0 0 0 0 0 0 0 0dreg
DIVU.L <ea>,Dh:DlDh:Dl÷<ea>→Dh,Dl--234S0 1 0 0 1 1 0 0 0 1smodsreg0qreg0 1 0 0 0 0 0 0 0rreg
DIVU.W <ea>,DdDd÷<ea>→Dd0123461 0 0 0dreg0 1 1smodsreg
DIVUL.L <ea>,Dh:DlDh:Dl÷<ea>→Dh,Dl--23460 1 0 0 1 1 0 0 0 1smodsreg0dlreg0 0 0 0 0 0 0 0 0dhreg
DOS <data>0123461 1 1 1 1 1 1 1data
EORI.B #<data>,CCR#<data>⊻CCR→CCR0123460 0 0 0 1 0 1 0 0 0 1 1 1 1 0 0
EORI.W #<data>,SR#<data>⊻SR→SR0123460 0 0 0 1 0 1 0 0 1 1 1 1 1 0 0
EOR.sz #<data>,<ea>#<data>⊻<ea>→<ea>0123460 0 0 0 1 0 1 0szdmoddreg
EOR.sz Dq,<ea>Dq⊻<ea>→<ea>0123461 0 1 1sreg 1szdmoddreg
EXG.L Aq,ArAq⇄Ar0123461 1 0 0dreg1 0 1 0 0 1sreg
EXG.L Dq,ArDq⇄Ar0123461 1 0 0dreg1 1 0 0 0 1sreg
EXG.L Dq,DrDq⇄Dr0123461 1 0 0dreg1 0 1 0 0 0sreg
EXT.L DrWord→Long0123460 1 0 0 1 0 0 0 1 1 0 0 0dreg
EXT.W DrByte→Word0123460 1 0 0 1 0 0 0 1 0 0 0 0dreg
EXTB.L DrByte→Long--23460 1 0 0 1 0 0 1 1 1 0 0 0dreg
FABS.FSZ <ea>,FPn|<ea>|→FPn--CC461 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg0 0 1 1 0 0 0
FABS.X FPm,FPn|FPm|→FPn--CC461 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg0 0 1 1 0 0 0
FACOS.FSZ <ea>,FPncos-1<ea>→FPn--CCSS1 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg0 0 1 1 1 0 0
FACOS.X FPm,FPncos-1FPm→FPn--CCSS1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg0 0 1 1 1 0 0
FADD.FSZ <ea>,FPn<ea>+FPn→FPn--CC461 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg0 1 0 0 0 1 0
FADD.X FPm,FPnFPm+FPn→FPn--CC461 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg0 1 0 0 0 1 0
FASIN.FSZ <ea>,FPnsin-1<ea>→FPn--CCSS1 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg0 0 0 1 1 0 0
FASIN.X FPm,FPnsin-1FPm→FPn--CCSS1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg0 0 0 1 1 0 0
FATAN.FSZ <ea>,FPntan-1<ea>→FPn--CCSS1 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg0 0 0 1 0 1 0
FATAN.X FPm,FPntan-1FPm→FPn--CCSS1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg0 0 0 1 0 1 0
FATANH.FSZ <ea>,FPntanh-1<ea>→FPn--CCSS1 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg0 0 0 1 1 0 1
FATANH.X FPm,FPntanh-1FPm→FPn--CCSS1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg0 0 0 1 1 0 1
Fbcc.L <label>if cc then PC+d→PC--CC461 1 1 1 0 0 1 0 1 1fcc
Fbcc.W <label>if cc then PC+d→PC--CC461 1 1 1 0 0 1 0 1 0fcc
FCMP.FSZ <ea>,FPnFPn-<ea>--CC461 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg0 1 1 1 0 0 0
FCMP.X FPm,FPnFPn-FPm--CC461 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg0 1 1 1 0 0 0
FCOS.FSZ <ea>,FPncos <ea>→FPn--CCSS1 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg0 0 1 1 1 0 1
FCOS.X FPm,FPncos FPm→FPn--CCSS1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg0 0 1 1 1 0 1
FCOSH.FSZ <ea>,FPncosh-1<ea>→FPn--CCSS1 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg0 0 1 1 0 0 1
FCOSH.X FPm,FPncosh-1FPm→FPn--CCSS1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg0 0 1 1 0 0 1
FDABS.FSZ <ea>,FPn|<ea>|→FPn----461 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg1 0 1 1 1 0 0
FDABS.X FPm,FPn|FPm|→FPn----461 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg1 0 1 1 1 0 0
FDADD.FSZ <ea>,FPn<ea>+FPn→FPn----461 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg1 1 0 0 1 1 0
FDADD.X FPm,FPnFPm+FPn→FPn----461 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg1 1 0 0 1 1 0
FDBcc Dr,<label>if !cc then Dn-1→Dn , if Dn≠-1 then PC+d→PC--CC4S1 1 1 1 0 0 1 0 0 1 0 0 1dreg0 0 0 0 0 0 0 0 0 0fcc
FDDIV.FSZ <ea>,FPnFPn÷<ea>→FPn----461 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg1 1 0 0 1 0 0
FDDIV.X FPm,FPnFPn÷FPm→FPn----461 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg1 1 0 0 1 0 0
FDIV.FSZ <ea>,FPnFPn÷<ea>→FPn--CC461 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg0 1 0 0 0 0 0
FDIV.X FPm,FPnFPn÷FPm→FPn--CC461 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg0 1 0 0 0 0 0
FDMOVE.FSZ <ea>,FPn<ea>→FPn----461 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg1 0 0 0 1 0 0
FDMOVE.X FPm,FPnFPm→FPn----461 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg1 0 0 0 1 0 0
FDMUL.FSZ <ea>,FPn<ea>*FPn→FPn----461 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg1 1 0 0 1 1 1
FDMUL.X FPm,FPnFPm*FPn→FPn----461 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg1 1 0 0 1 1 1
FDNEG.FSZ <ea>,FPn-<ea>→FPn----461 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg1 0 1 1 1 1 0
FDNEG.X FPm,FPn-FPm→FPn----461 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg1 0 1 1 1 1 0
FDSQRT.FSZ <ea>,FPn√(<ea>)→FPn----461 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg1 0 0 0 1 0 1
FDSQRT.X FPm,FPn√(FPm)→FPn----461 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg1 0 0 0 1 0 1
FDSUB.FSZ <ea>,FPnFPn-<ea>→FPn----461 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg1 1 0 1 1 0 0
FDSUB.X FPm,FPnFPn-FPm→FPn----461 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg1 1 0 1 1 0 0
FETOX.FSZ <ea>,FPne<ea>→FPn--CCSS1 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg0 0 1 0 0 0 0
FETOX.X FPm,FPneFPm→FPn--CCSS1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg0 0 1 0 0 0 0
FETOXM1.FSZ <ea>,FPne<ea>-1→FPn--CCSS1 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg0 0 0 1 0 0 0
FETOXM1.X FPm,FPneFPm-1→FPn--CCSS1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg0 0 0 1 0 0 0
FGETEXP.FSZ <ea>,FPn<ea>の指数→FPn--CCSS1 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg0 0 1 1 1 1 0
FGETEXP.X FPm,FPnFPmの指数→FPn--CCSS1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg0 0 1 1 1 1 0
FGETMAN.FSZ <ea>,FPn<ea>の仮数→FPn--CCSS1 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg0 0 1 1 1 1 1
FGETMAN.X FPm,FPnFPmの仮数→FPn--CCSS1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg0 0 1 1 1 1 1
FINT.FSZ <ea>,FPn整数部の切り出し(<ea>)→FPn--CCS61 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg0 0 0 0 0 0 1
FINTRZ.FSZ <ea>,FPn整数部の切り出し 0に丸める(<ea>)→FPn--CCS61 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg0 0 0 0 0 1 1
FINTRZ.X FPm,FPn整数部の切り出し 0に丸める(FPm)→FPn--CCS61 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg0 0 0 0 0 1 1
FLINE #<data>0123461 1 1 1d12
FLOG10.FSZ <ea>,FPnLog10(<ea>)→FPn--CCSS1 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg0 0 1 0 1 0 1
FLOG10.X FPm,FPnLog10(FPm)→FPn--CCSS1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg0 0 1 0 1 0 1
FLOG2.FSZ <ea>,FPnLog2(<ea>)→FPn--CCSS1 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg0 0 1 0 1 1 0
FLOG2.X FPm,FPnLog2(FPm)→FPn--CCSS1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg0 0 1 0 1 1 0
FLOGN.FSZ <ea>,FPnln(<ea>)→FPn--CCSS1 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg0 0 1 0 1 0 0
FLOGN.X FPm,FPnln(FPm)→FPn--CCSS1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg0 0 1 0 1 0 0
FLOGNP1.FSZ <ea>,FPnln(<ea>+1)→FPn--CCSS1 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg0 0 0 0 1 1 0
FLOGNP1.X FPm,FPnln(FPm+1)→FPn--CCSS1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg0 0 0 0 1 1 0
FMOD.FSZ <ea>,FPnFPn%<ea>→FPn--CCSS1 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg0 1 0 0 0 0 1
FMOD.X FPm,FPnFPn%FPm→FPn--CCSS1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg0 1 0 0 0 0 1
FMOVE.FSZ <ea>,FPn<ea>→FPn--CC461 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg0 0 0 0 0 0 0
FMOVE.FSZ FPn,<ea>FPn→<ea>--CC461 1 1 1 0 0 1 0 0 0dmoddreg0 1 1Fszsreg0 0 0 0 0 0 0
FMOVE.L <ea>,FPCR/FPSR/FPIAR<ea>→FPCR/FPSR/FPIAR--CC461 1 1 1 0 0 1 0 0 0smodsreg1 0 0list0 0 0 0 0 0 0 0 0 0
FMOVE.L FPCR/FPSR/FPIAR,<ea>FPCR/FPSR/FPIAR→<ea>--CC461 1 1 1 0 0 1 0 0 0smodsreg1 0 1list0 0 0 0 0 0 0 0 0 0
FMOVE.P FPn,<ea>{#k}FPn→<ea> #kで丸める--CCSS1 1 1 1 0 0 1 0 0 0smodsreg0 1 1 0 1 1sregk
FMOVE.P FPn,<ea>{Dk}FPn→<ea> Dkで丸める--CCSS1 1 1 1 0 0 1 0 0 0smodsreg0 1 1 1 1 1sregk0 0 0 0
FMOVECR.X #ccc,FPn定数→FPn--CCSS1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 1 0 1 1 1dregROM Offset
FMOVEM.L #<data>,
#<data>,FPCR/FPSR/FPIAR		{#<data>}→FPCR/FPSR/FPIAR--CC4S1 1 1 1 0 0 1 0 0 0 1 1 1 1 0 01 0 0list0 0 0 0 0 0 0 0 0 0
FMOVEM.L #<data>,
#<data>,#<data>,FPCR/FPSR/FPIAR		{#<data>}→FPCR/FPSR/FPIAR--CC4S1 1 1 1 0 0 1 0 0 0 1 1 1 1 0 01 0 0list0 0 0 0 0 0 0 0 0 0
FMOVEM.L #<data>,
#<data>,#<data>,#<data>,FPCR/FPSR/FPIAR		{#<data>}→FPCR/FPSR/FPIAR--CC4S1 1 1 1 0 0 1 0 0 0 1 1 1 1 0 01 0 0list0 0 0 0 0 0 0 0 0 0
FMOVEM.L <ea>,FPSR/FPSR/FPIAR<ea>→FPCR/FPSR/FPIAR--CC461 1 1 1 0 0 1 0 0 0smodsreg1 0 0list0 0 0 0 0 0 0 0 0 0
FMOVEM.L FPSR/FPSR/FPIAR,<ea>FPCR/FPSR/FPIAR→<ea>--CC461 1 1 1 0 0 1 0 0 0smodsreg1 0 1list0 0 0 0 0 0 0 0 0 0
FMOVEM.L #<data>,FPCR/FPSR/FPIAR{#<data>}→FPCR/FPSR/FPIAR--CC4S1 1 1 1 0 0 1 0 0 0 1 1 1 1 0 01 0 0list0 0 0 0 0 0 0 0 0 0
FMOVEM.L #<data>,#<data>,FPCR/FPSR/FPIAR{#<data>}→FPCR/FPSR/FPIAR--CC4S1 1 1 1 0 0 1 0 0 0 1 1 1 1 0 01 0 0list0 0 0 0 0 0 0 0 0 0
FMOVEM.L #<data>,#<data>,#<data>,FPCR/FPSR/FPIAR{#<data>}→FPCR/FPSR/FPIAR--CC4S1 1 1 1 0 0 1 0 0 0 1 1 1 1 0 01 0 0list0 0 0 0 0 0 0 0 0 0
FMOVEM.L <ea>,FPCR/FPSR/FPIAR<ea>→FPCR--CC461 1 1 1 0 0 1 0 0 0smodsreg1 0 0list0 0 0 0 0 0 0 0 0 0
FMOVEM.L FPCR/FPSR/FPIAR,<ea>FPCR/FPSR/FPIAR→<ea>--CC461 1 1 1 0 0 1 0 0 0smodsreg1 0 1list0 0 0 0 0 0 0 0 0 0
FMOVEM.X <ea>,<flist><ea>→Register List--CC461 1 1 1 0 0 1 0 0 0smodsreg1 1 01 00 0 0flist
FMOVEM.X (Ar)+,<flist>(Ar)+→Register List--CC461 1 1 1 0 0 1 0 0 0smodsreg1 1 01 00 0 0flist
FMOVEM.X <ea>,Dl<ea>→Dl(Register List)--CC4S1 1 1 1 0 0 1 0 0 0smodsreg1 1 01 10 0 0 0dreg0 0 0 0
FMOVEM.X (Ar)+,Dl(Ar)+→Dl(Register List)--CC4S1 1 1 1 0 0 1 0 0 0smodsreg1 1 01 10 0 0 0dreg0 0 0 0
FMOVEM.X <flist>,-(Ar)Register List→-(Ar)--CC461 1 1 1 0 0 1 0 0 0 1 0 0dreg1 1 10 00 0 0flist
FMOVEM.X <flist>,<ea>Register List→<ea>--CC461 1 1 1 0 0 1 0 0 0smodsreg1 1 10 00 0 0flist
FMOVEM.X Dl,-(Ar)Dl(Register List)→-(Ar)--CC4S1 1 1 1 0 0 1 0 0 0 1 0 0dreg1 1 10 10 0 0 0sreg0 0 0 0
FMOVEM.X Dl,<ea>Dl(Register List)→<ea>--CC4S1 1 1 1 0 0 1 0 0 0dmoddreg1 1 10 10 0 0 0sreg0 0 0 0
FMUL.FSZ <ea>,FPn<ea>*FPn→FPn--CC461 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg0 1 0 0 0 1 1
FMUL.X FPm,FPnFPm*FPn→FPn--CC461 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg0 1 0 0 0 1 1
FNEG.FSZ <ea>,FPn-<ea>→FPn--CC461 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg0 0 1 1 0 1 0
FNEG.X FPm,FPn-FPm→FPn--CC461 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg0 0 1 1 0 1 0
FNOP--CC461 1 1 1 0 0 1 0 1 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FPACK <data>FLINE0123461 1 1 1 1 1 1 0d8
FREM.FSZ <ea>,FPnFPn%<ea>→FPn IEEE--CCSS1 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg0 1 0 0 1 0 1
FREM.X FPm,FPnFPn%FPm→FPn IEEE--CCSS1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg0 1 0 0 1 0 1
FRESTORE <ea>Restore Internal FRESTORE Floating-Point State--CC461 1 1 1 0 0 1 1 0 1smodsreg
FSABS.FSZ <ea>,FPn|<ea>|→FPn----461 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg1 0 1 1 0 0 0
FSABS.X FPm,FPn|FPm|→FPn----461 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg1 0 1 1 0 0 0
FSADD.FSZ <ea>,FPn<ea>+FPn→FPn----461 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg1 1 0 0 0 1 0
FSADD.X FPm,FPnFPm+FPn→FPn----461 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg1 1 0 0 0 1 0
FSAVE <ea>Save Internal Floating-Point State--CC461 1 1 1 0 0 1 1 0 0smodsreg
FSCALE.FSZ <ea>,FPnFPn*INT(2<ea>)→FPn--CCSS1 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg0 1 0 0 1 1 0
FSCALE.X FPm,FPnFPn*INT(2FPm)→FPn--CCSS1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg0 1 0 0 1 1 0
FSDIV.FSZ <ea>,FPnFPn÷<ea>→FPn----461 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg1 1 0 0 0 0 0
FSDIV.X FPm,FPnFPn÷FPm→FPn----461 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg1 1 0 0 0 0 0
FSGLDIV.FSZ <ea>,FPnFPn÷<ea>→FPn--CCS61 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg0 1 0 0 1 0 0
FSGLDIV.X FPm,FPnFPn÷FPm→FPn--CCS61 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg0 1 0 0 1 0 0
FSGLMUL.FSZ <ea>,FPnFPn*<ea>→FPn--CCS61 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg0 1 0 0 1 1 1
FSGLMUL.X FPm,FPnFPn*FPm→FPn--CCS61 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg0 1 0 0 1 1 1
FSIN.FSZ <ea>,FPnsin <ea>→FPn--CCSS1 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg0 0 0 1 1 1 0
FSIN.X FPm,FPnsin FPm→FPn--CCSS1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg0 0 0 1 1 1 0
FSINCOS.FSZ <ea>,FPc:FPscos <ea>→FPc,sin <ea>→FPs--CCSS1 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszregs0 1 1 0regc
FSINCOS.X FPm,FPc:FPscos FPm→FPc,sin FPm→FPs--CCSS1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregregs0 1 1 0regc
FSINH.FSZ <ea>,FPnsinh <ea>→FPn--CCSS1 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg0 0 0 0 0 1 0
FSINH.X FPm,FPnsinh FPm→FPn--CCSS1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg0 0 0 0 0 1 0
FScc.B <ea>cc ? 1 : 0→<ea>--CC4S1 1 1 1 0 0 1 0 0 1smodsreg0 0 0 0 0 0 0 0 0 0fcc
FSNEG.FSZ <ea>,FPn|<ea>|→FPn----461 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg1 0 1 1 0 1 0
FSNEG.X FPm,FPn|FPm|→FPn----461 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg1 0 1 1 0 1 0
FSMOVE.FSZ <ea>,FPn<ea>→FPn----461 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg1 0 0 0 0 0 0
FSMOVE.X FPm,FPnFPm→FPn----461 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg1 0 0 0 0 0 0
FSMUL.FSZ <ea>,FPn<ea>*FPn→FPn----461 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg1 1 0 0 0 1 1
FSMUL.X FPm,FPnFPm*FPn→FPn----461 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg1 1 0 0 0 1 1
FSQRT.FSZ <ea>,FPn√(<ea>)→FPn--CC461 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg0 0 0 0 1 0 0
FSQRT.X FPm,FPn√(FPm)→FPn--CC461 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg0 0 0 0 1 0 0
FSSQRT.FSZ <ea>,FPn√(<ea>)→FPn----461 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg1 0 0 0 0 0 1
FSSQRT.X FPm,FPn√(<ea>)→FPn----461 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg1 0 0 0 0 0 1
FSSUB.FSZ <ea>,FPnFPn-<ea>→FPn----461 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg1 1 0 1 0 0 0
FSSUB.X FPm,FPnFPn-FPm→FPn----461 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg1 1 0 1 0 0 0
FSUB.FSZ <ea>,FPnFPn-<ea>→FPn--CC461 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg0 1 0 1 0 0 0
FSUB.X FPm,FPnFPn-FPm→FPn--CC461 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg0 1 0 1 0 0 0
FTAN.FSZ <ea>,FPntan <ea>→FPn--CCSS1 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg0 0 0 1 1 1 1
FTAN.B <ea>,FPntan <ea>→FPn--CCSS1 1 1 1 0 0 1 0 0 0smodsreg0 1 0 1 1 0dreg0 0 0 1 1 1 1
FTAN.X FPm,FPntan FPm→FPn--CCSS1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg0 0 0 1 0 0 1
FTANH.FSZ <ea>,FPnfanh <ea>→FPn--CCSS1 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg0 0 0 1 0 0 1
FTANH.X FPm,FPntanh FPm→FPn--CCSS1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg0 0 0 1 0 0 1
FTENTOX.FSZ <ea>,FPn10<ea>→FPn--CCSS1 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg0 0 1 0 0 1 0
FTENTOX.X FPm,FPn10FPm→FPn--CCSS1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg0 0 1 0 0 1 0
FTRAPccif cc then trap--CC4S1 1 1 1 0 0 1 0 0 1 1 1 1mod0 0 0 0 0 0 0 0 0 0fcc
FTST.FSZ <ea>Condition Codes for Operand → FPCC--CC461 1 1 1 0 0 1 0 0 0dmoddreg0 1 0Fsz0 0 0 0 1 1 1 0 1 0
FTST.X FPmCondition Codes for Operand → FPCC--CC461 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0dreg0 0 0 0 1 1 1 0 1 0
FTWOTOX.FSZ <ea>,FPn2<ea>→FPn--CCSS1 1 1 1 0 0 1 0 0 0smodsreg0 1 0Fszdreg0 0 1 0 0 0 1
FTWOTOX.X FPm,FPn2FPm→FPn--CCSS1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 00 0 0sregdreg0 0 1 0 0 0 1
ILLEGAL未定義命令トラップ0123460 1 0 0 1 0 1 0 1 1 1 1 1 1 0 0
JMP <ea>0123460 1 0 0 1 1 1 0 1 1dmoddreg
JSR <ea>0123460 1 0 0 1 1 1 0 1 0dmoddreg
LEA.L <ea>,Aq<ea>→An0123460 1 0 0dreg1 1 1smodsreg
LINK.L Ar,#<data>SP-4→SP An→(SP) SP+data→SP--23460 1 0 0 1 0 0 0 0 0 0 0 1dreg
LINK.W Ar,#<data>SP-4→SP An→(SP) SP+data→SP0123460 1 0 0 1 1 1 0 0 1 0 1 0dreg
LPSTOP.W #<data>Low-Power Stop-----61 1 1 1 1 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0
LSL.sz #<data>,Dr論理左シフト0123461 1 1 0data 1sz0 0 1dreg
LSL.sz Dq,Dr0123461 1 1 0sreg 1sz1 0 1dreg
LSL.sz Dr0123461 1 1 0 0 0 1 1sz0 0 1dreg
LSL.W <ea>0123461 1 1 0 0 0 1 1 1 1dmoddreg
LSR.sz #<data>,Dr論理右シフト0123461 1 1 0data 0sz0 0 1dreg
LSR.sz Dq,Dr0123461 1 1 0sreg 0sz1 0 1dreg
LSR.sz Dr0123461 1 1 0 0 0 1 0sz0 0 1dreg
LSR.W <ea>0123461 1 1 0 0 0 1 0 1 1dmoddreg
MOVE.L Ar,USPAr→USP0123460 1 0 0 1 1 1 0 0 1 1 0 0sreg
MOVE.L USP,ArUSP→Ar0123460 1 0 0 1 1 1 0 0 1 1 0 1dreg
MOVE.SZ src,dtcsrc→dtc0123460 0szdregdmodsmodsreg
MOVE.W <ea>,CCR<ea>→CCR0123460 1 0 0 0 1 0 0 1 1smodsreg
MOVE.W <ea>,SR<ea>→SR0123460 1 0 0 0 1 1 0 1 1smodsreg
MOVE.W CCR,<ea>CCR→<ea>-123460 1 0 0 0 0 1 0 1 1dmoddreg
MOVE.W SR,<ea>SR→<ea>-123460 1 0 0 0 0 0 0 1 1dmoddreg
MOVE16 (Ar),xxx.L(Ar)→xxx.L 16byte----461 1 1 1 0 1 1 0 0 0 0 1 0sreg
MOVE16 (Ar)+,(An)+(Ar)+ → (An)+ 16byte----461 1 1 1 0 1 1 0 0 0 1 0 0sreg1dreg0 0 0 0 0 0 0 0 0 0 0 0
MOVE16 (Ar)+,xxx.L(Ar)+ → xxx.L 16byte----461 1 1 1 0 1 1 0 0 0 0 0 0sreg
MOVE16 xxx.L,(Ar)xxx.L → (Ar) 16byte----461 1 1 1 0 1 1 0 0 0 0 1 1dreg
MOVE16 xxx.L,(Ar)+xxx.L → (Ar)+ 16byte----461 1 1 1 0 1 1 0 0 0 0 0 1dreg
MOVEA.L <ea>,Aq<ea>→Aq0123460 0 1 0dreg0 0 1smodsreg
MOVEA.W <ea>,Aq<ea>→Aq0123460 0 1 1dreg0 0 1smodsreg
MOVEC.L Rc,RnRc→Rn-123460 1 0 0 1 1 1 0 0 1 1 1 1 0 1 0dancr
MOVEC.L Rn,RcRn→Rc-123460 1 0 0 1 1 1 0 0 1 1 1 1 0 1 1dancr
MOVEM.L <ea>,<list><ea>→Listed Registers0123460 1 0 0 1 1 0 0 1 1smodsregrlist
MOVEM.L <list>,<ea>Listed Registers→<ea>0123460 1 0 0 1 0 0 0 1 1dmoddregrlist
MOVEM.W <ea>,<list><ea>→Listed Registers0123460 1 0 0 1 1 0 0 1 0smodsregrlist
MOVEM.W <list>,<ea>Listed Registers→<ea>0123460 1 0 0 1 0 0 0 1 0dmoddregrlist
MOVEP.L (d16,Ar),Dq<ea>→Dq[31_24],
<ea+2>→Dq[23_16],
<ea+4>→Dq[15_8],
<ea+6>→Dq[7_0]		01234S0 0 0 0dreg1 0 1 0 0 1sreg
MOVEP.L Dq,(d16,Ar)Dq[31_24]→<ea>,
Dq[23_16]→<ea+2>,
Dq[15_8]→<ea+4>,
Dq[7_0]→<ea+6>		01234S0 0 0 0sreg1 1 1 0 0 1dreg
MOVEP.W (d16,Ar),Dq<ea+2>→Dq[15_8],
<ea>→Dq[7_0]		01234S0 0 0 0sreg1 0 0 0 0 1dreg
MOVEP.W Dq,(d16,Ar)Dq[15_8]→<ea+2>,
Dq[7_0]→<ea>		01234S0 0 0 0sreg1 1 0 0 0 1dreg
MOVEQ.L #<data>,Dq#<data>→Dq0123460 1 1 1dreg 0data
MOVES.sz <ea>,RnUsing SFC <ea>→Rn-123460 0 0 0 1 1 1 0szsmodsregdadreg0 0 0 0 0 0 0 0 0 0 0 0
MOVES.sz Rn,<ea>Rn→<ea> Using DFC-123460 0 0 0 1 1 1 0szdmoddregdasreg1 0 0 0 0 0 0 0 0 0 0 0
MULS.L <ea>,Dh:Dl<ea>*Dl→Dh:Dl--234S0 1 0 0 1 1 0 0 0 0smodsreg0dlreg1 1 0 0 0 0 0 0 0dhreg
MULS.L <ea>,Dl<ea>*Dl→Dl--23460 1 0 0 1 1 0 0 0 0smodsreg0dlreg1 0 0 0 0 0 0 0 0dhreg
MULS.W <ea>,Dq<ea>*Dq→Dq0123461 1 0 0dreg1 1 1smodsreg
MULU.L <ea>,Dh:Dl<ea>*Dl→Dh:Dl--234S0 1 0 0 1 1 0 0 0 0smodsreg0dlreg0 1 0 0 0 0 0 0 0dhreg
MULU.L <ea>,Dl<ea>*Dl→Dl--23460 1 0 0 1 1 0 0 0 0smodsreg0dlreg0 0 0 0 0 0 0 0 0dhreg
MULU.W <ea>,Dq<ea>*Dq→Dq0123461 1 0 0dreg0 1 1smodsreg
NBCD.B <ea>0-<ea>-X→<ea>0123460 1 0 0 1 0 0 0 0 0dmoddreg
NEG.sz <ea>0-<ea>→<ea>0123460 1 0 0 0 1 0 0szdmoddreg
NEGXsz <ea>0-<ea>-X→<ea>0123460 1 0 0 0 0 0 0szdmoddreg
NOP0123460 1 0 0 1 1 1 0 0 1 1 1 0 0 0 1
NOT.sz <ea>~<ea>→<ea>0123460 1 0 0 0 1 1 0szdmoddreg
OR.sz #<data>,<ea>#<data>∨<ea>→<ea>0123460 0 0 0 0 0 0 0szdmoddreg
OR.sz <ea>,Dq<ea>∨Dq→Dq0123461 0 0 0dreg 0szsmodsreg
OR.sz Dq,<ea>Dq∨<ea>→<ea>0123461 0 0 0dreg 1szdmoddreg
ORI.B #<data>,CCR#<data>∨CCR→CCR0123460 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0
ORI.W #<data>,SR#<data>∨SR→SR0123460 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0
PACK -(Ar),-(Aq),#<data>Pack BCD--23461 0 0 0dreg1 0 1 0 0 1sreg
PACK Dr,Dq,#<data>Pack BCD--23461 0 0 0dreg1 0 1 0 0 0sreg
PBcc.L <label>Branch on PMMU Condition--M---1 1 1 1 0 0 0 0 1 1pcc
PBcc.W <label>Branch on PMMU Condition--M---1 1 1 1 0 0 0 0 1 0pcc
PDBcc Dr,<label>Test, Decrement, and Branch on PMMU Condition--M---1 1 1 1 0 0 0 0 0 1 0 0 1sreg0 0 0 0 0 0 0 0 0 0pcc
PEA.L <ea>SP-4→SP <ea>→(SP)0123460 1 0 0 1 0 0 0 0 1smodsreg
PFLUSH (Ar)Flush Entry(ies) in the ATCs----461 1 1 1 0 1 0 1 0 0 0 0 1sreg
PFLUSH #<data>,#<mask>Flush Entry(ies) in the ATCs---3--1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 00 0 1 1 0 0 0 0m1 0data
PFLUSH #<data>,#<mask>Flush Entry(ies) in the ATCs--M---1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 00 0 1 1 0 0 0m 1data
PFLUSH #<data>,#<mask>,<ea>Flush Entry(ies) in the ATCs---3--1 1 1 1 0 0 0 0 0 0dmoddreg0 0 1 1 1 0 0 0m1 0data
PFLUSH #<data>,#<mask>,<ea>Flush Entry(ies) in the ATCs--M---1 1 1 1 0 0 0 0 0 0dmoddreg0 0 1 1 1 0 0m 1data
PFLUSH DFC,#<mask>Flush Entry(ies) in the ATCs---3--1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 00 0 1 1 0 0 0 0m0 0 0 0 1
PFLUSH DFC,#<mask>Flush Entry(ies) in the ATCs--M---1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 00 0 1 1 0 0 0m0 0 0 0 1
PFLUSH DFC,#<mask>,<ea>Flush Entry(ies) in the ATCs---3--1 1 1 1 0 0 0 0 0 0dmoddreg0 0 1 1 1 0 0 0m0 0 0 0 1
PFLUSH DFC,#<mask>,<ea>Flush Entry(ies) in the ATCs--M---1 1 1 1 0 0 0 0 0 0dmoddreg0 0 1 1 1 0 0m0 0 0 0 1
PFLUSH Dn,#<mask>Flush Entry(ies) in the ATCs---3--1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 00 0 1 1 0 0 0 0m0 1dreg
PFLUSH Dn,#<mask>Flush Entry(ies) in the ATCs--M---1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 00 0 1 1 0 0 0m0 1dreg
PFLUSH Dn,#<mask>,<ea>Flush Entry(ies) in the ATCs---3--1 1 1 1 0 0 0 0 0 0dmoddreg0 0 1 1 1 0 0 0m0 1dreg
PFLUSH Dn,#<mask>,<ea>Flush Entry(ies) in the ATCs--M---1 1 1 1 0 0 0 0 0 0dmoddreg0 0 1 1 1 0 0m0 1dreg
PFLUSH SFC,#<mask>Flush Entry(ies) in the ATCs---3--1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 00 0 1 1 0 0 0 0m0 0 0 0 0
PFLUSH SFC,#<mask>Flush Entry(ies) in the ATCs--M---1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 00 0 1 1 0 0 0m0 0 0 0 0
PFLUSH SFC,#<mask>,<ea>Flush Entry(ies) in the ATCs---3--1 1 1 1 0 0 0 0 0 0dmoddreg0 0 1 1 1 0 0 0m0 0 0 0 0
PFLUSH SFC,#<mask>,<ea>Flush Entry(ies) in the ATCs--M---1 1 1 1 0 0 0 0 0 0dmoddreg0 0 1 1 1 0 0m0 0 0 0 0
PFLUSHAFlush Entry(ies) in the ATCs---3--1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 00 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0
PFLUSHAFlush Entry(ies) in the ATCs--M---1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 00 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0
PFLUSHAFlush Entry(ies) in the ATCs----461 1 1 1 0 1 0 1 0 0 0 1 1 0 0 0
PFLUSHANFlush Entry(ies) in the ATCs----461 1 1 1 0 1 0 1 0 0 0 1 0 0 0 0
PFLUSHN (Ar)Flush Entry(ies) in the ATCs----461 1 1 1 0 1 0 1 0 0 0 0 0dreg
PFLUSHR <ea>Flush Entry(ies) in the ATCs--M---1 1 1 1 0 0 0 0 0 0dmoddreg1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
PFLUSHS #<data>,#<mask>Flush Entry(ies) in the ATCs--M---1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 00 0 1 1 0 1 0m 1d
PFLUSHS #<data>,#<mask>,<ea>Flush Entry(ies) in the ATCs--M---1 1 1 1 0 0 0 0 0 0dmoddreg0 0 1 1 1 1 0m 1d
PFLUSHS DFC,#<mask>Flush Entry(ies) in the ATCs--M---1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 00 0 1 1 0 1 0m0 0 0 0 1
PFLUSHS DFC,#<mask>,<ea>Flush Entry(ies) in the ATCs--M---1 1 1 1 0 0 0 0 0 0dmoddreg0 0 1 1 1 1 0m0 0 0 0 1
PFLUSHS Dn,#<mask>Flush Entry(ies) in the ATCs--M---1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 00 0 1 1 0 1 0m0 1n
PFLUSHS Dn,#<mask>,<ea>Flush Entry(ies) in the ATCs--M---1 1 1 1 0 0 0 0 0 0dmoddreg0 0 1 1 0 1 0m0 1n
PFLUSHS SFC,#<mask>Flush Entry(ies) in the ATCs--M---1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 00 0 1 1 0 1 0m0 0 0 0 0
PFLUSHS SFC,#<mask>,<ea>Flush Entry(ies) in the ATCs--M---1 1 1 1 0 0 0 0 0 0dmoddreg0 0 1 1 1 1 0m0 0 0 0 0
PLOADR #<data>,<ea>Load an Entry into the ATC---3--1 1 1 1 0 0 0 0 0 0dmoddreg0 0 1 0 0 0 1 0 0 0 0 1 0data
PLOADR #<data>,<ea>Load an Entry into the ATC--M---1 1 1 1 0 0 0 0 0 0dmoddreg0 0 1 0 0 0 1 0 0 0 0 1d
PLOADR DFC,<ea>Load an Entry into the ATC--|m3|--1 1 1 1 0 0 0 0 0 0dmoddreg0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1
PLOADR Dn,<ea>Load an Entry into the ATC--|m3|--1 1 1 1 0 0 0 0 0 0dmoddreg0 0 1 0 0 0 1 0 0 0 0 0 1n
PLOADR SFC,<ea>Load an Entry into the ATC--|m3|--1 1 1 1 0 0 0 0 0 0dmoddreg0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0
PLOADW #<data>,<ea>Load an Entry into the ATC---3--1 1 1 1 0 0 0 0 0 0dmoddreg0 0 1 0 0 0 0 0 0 0 0 1 0data
PLOADW #<data>,<ea>Load an Entry into the ATC--M---1 1 1 1 0 0 0 0 0 0dmoddreg0 0 1 0 0 0 0 0 0 0 0 1d
PLOADW DFC,<ea>Load an Entry into the ATC--|m3|--1 1 1 1 0 0 0 0 0 0dmoddreg0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1
PLOADW Dn,<ea>Load an Entry into the ATC--|m3|--1 1 1 1 0 0 0 0 0 0dmoddreg0 0 1 0 0 0 0 0 0 0 0 0 1n
PLOADW SFC,<ea>Load an Entry into the ATC--|m3|--1 1 1 1 0 0 0 0 0 0dmoddreg0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
PLPAR (Ar)Load Physical Address-----61 1 1 1 0 1 0 1 1 1 0 0 1dreg
PLPAW (Ar)Load Physical Address-----61 1 1 1 0 1 0 1 1 0 0 0 1dreg
PMOVE <ea>,TC/CAL/VAL/SCC/AC/PSR/DRP/CRP<ea>→TC/CAL/VAL/SCC/AC/PSR/DRP/CRP--3M---1 1 1 1 0 0 0 0 0 0smodsreg0 1 0mreg0 0 0 0 0 0 0 0 0 0
PMOVE.L <ea>,TTn<ea>→TTn---3--1 1 1 1 0 0 0 0 0 0smodsreg0 0 0 0 1n0 0 0 0 0 0 0 0 0 0
PMOVE.L TC/CAL/VAL/SCC/AC/PSR/DRP/CRP,<ea>TC/CAL/VAL/SCC/AC/PSR/DRP/CRP→<ea>--3M---1 1 1 1 0 0 0 0 0 0dmoddreg0 1 0mreg1 0 0 0 0 0 0 0 0 0
PMOVE.L TTn,<ea>TTn→<ea>---3--1 1 1 1 0 0 0 0 0 0dmoddreg0 0 0 0 1n1 0 0 0 0 0 0 0 0 0
PMOVE.W <ea>,BACn<ea>→BACn--M---1 1 1 1 0 0 0 0 0 0smodsreg0 1 1 1 0 1 0 0 0 0 0n0 0
PMOVE.W <ea>,BADn<ea>→BADn--M---1 1 1 1 0 0 0 0 0 0smodsreg0 1 1 1 0 0 0 0 0 0 0n0 0
PMOVE.W <ea>,MMUSR<ea>→MMUSR---3--1 1 1 1 0 0 0 0 0 0smodsreg0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
PMOVE.W <ea>,PCSR<ea>→PCSR--M---1 1 1 1 0 0 0 0 0 0smodsreg0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0
PMOVE.W <ea>,PSR<ea>→PSR--M---1 1 1 1 0 0 0 0 0 0smodsreg0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
PMOVE.W BACn,<ea>BACn→<ea>--M---1 1 1 1 0 0 0 0 0 0dmoddreg0 1 1 1 0 1 1 0 0 0 0n0 0
PMOVE.W BADn,<ea>BADn→<ea>--M---1 1 1 1 0 0 0 0 0 0dmoddreg0 1 1 1 0 0 1 0 0 0 0n0 0
PMOVE.W MMUSR,<ea>MMUSR→<ea>---3--1 1 1 1 0 0 0 0 0 0dmoddreg0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0
PMOVE.W PCSR,<ea>PCSR→<ea>--M---1 1 1 1 0 0 0 0 0 0dmoddreg0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0
PMOVE.W PSR,<ea>PSR→<ea>--M---1 1 1 1 0 0 0 0 0 0smodsreg0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0
PMOVEFD.L <ea>,TC<ea>→TC---3--1 1 1 1 0 0 0 0 0 0smodsreg0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0
PMOVEFD.L <ea>,TTn<ea>→TTn---3--1 1 1 1 0 0 0 0 0 0smodsreg0 0 0 0 1n0 1 0 0 0 0 0 0 0 0
PMOVEFD.Q <ea>,CRP<ea>→CRP---3--1 1 1 1 0 0 0 0 0 0smodsreg0 1 0 0 1 1 0 1 0 0 0 0 0 0 0 0
PMOVEFD.Q <ea>,SRP<ea>→SRP---3--1 1 1 1 0 0 0 0 0 0smodsreg0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0
PRESTORE <ea>PMMU Restore Function--M---1 1 1 1 0 0 0 1 0 1smodsreg
PScc.B <ea>Set on PMMU Condition--M---1 1 1 1 0 0 0 0 0 1dmoddreg0 0 0 0 0 0 0 0 0 0 0pcc
PSAVE <ea>PMMU Save Function--M---1 1 1 1 0 0 0 1 0 0dmoddreg
PTESTR (Ar)Test a Logical Address----4-1 1 1 1 0 1 0 1 0 1 1 0 1dreg
PTESTR #<data>,<ea>,#<level>Test a Logical Address---3--1 1 1 1 0 0 0 0 0 0dmoddreg1 0 0level1 0 0 0 0 1 0data
PTESTR #<data>,<ea>,#<level>,AnTest a Logical Address---3--1 1 1 1 0 0 0 0 0 0dmoddreg1 0 0level1 1n1 0data
PTESTR DFC,<ea>,#<level>Test a Logical Address---3--1 1 1 1 0 0 0 0 0 0dmoddreg1 0 0level1 0 0 0 0 0 0 0 0 1
PTESTR DFC,<ea>,#<level>,AnTest a Logical Address---3--1 1 1 1 0 0 0 0 0 0dmoddreg1 0 0level1 1n0 0 0 0 1
PTESTR Dn,<ea>,#<level>Test a Logical Address---3--1 1 1 1 0 0 0 0 0 0dmoddreg1 0 0level1 0 0 0 0 0 1sreg
PTESTR Dn,<ea>,#<level>,AnTest a Logical Address---3--1 1 1 1 0 0 0 0 0 0dmoddreg1 0 0level1 1n0 1sreg
PTESTR SFC,<ea>,#<level>Test a Logical Address---3--1 1 1 1 0 0 0 0 0 0dmoddreg1 0 0level1 0 0 0 0 0 0 0 0 0
PTESTR SFC,<ea>,#<level>,AnTest a Logical Address---3--1 1 1 1 0 0 0 0 0 0dmoddreg1 0 0level1 1n0 0 0 0 0
PTESTR #<data>,<ea>,#<level>Test a Logical Address--M---1 1 1 1 0 0 0 0 0 0dmoddreg1 0 0level1 0 0 0 0 1data
PTESTR #<data>,<ea>,#<level>,AnTest a Logical Address--M---1 1 1 1 0 0 0 0 0 0dmoddreg1 0 0level1 1n 1data
PTESTR DFC,<ea>,#<level>Test a Logical Address--M---1 1 1 1 0 0 0 0 0 0dmoddreg1 0 0level1 0 0 0 0 0 0 0 0 1
PTESTR DFC,<ea>,#<level>,AnTest a Logical Address--M---1 1 1 1 0 0 0 0 0 0dmoddreg1 0 0level1 1n0 0 0 0 1
PTESTR Dn,<ea>,#<level>Test a Logical Address--M---1 1 1 1 0 0 0 0 0 0dmoddreg1 0 0level1 0 0 0 0 0 1sreg
PTESTR Dn,<ea>,#<level>,AnTest a Logical Address--M---1 1 1 1 0 0 0 0 0 0dmoddreg1 0 0level1 1n0 1sreg
PTESTR SFC,<ea>,#<level>Test a Logical Address--M---1 1 1 1 0 0 0 0 0 0dmoddreg1 0 0level1 0 0 0 0 0 0 0 0 0
PTESTR SFC,<ea>,#<level>,AnTest a Logical Address--M---1 1 1 1 0 0 0 0 0 0dmoddreg1 0 0level1 1n0 0 0 0 0
PTESTW (Ar)Test a Logical Address----4-1 1 1 1 0 1 0 1 0 1 0 0 1dreg
PTESTW #<data>,<ea>,#<level>Test a Logical Address---3--1 1 1 1 0 0 0 0 0 0dmoddreg1 0 0level0 0 0 0 0 1 0data
PTESTW #<data>,<ea>,#<level>,AnTest a Logical Address---3--1 1 1 1 0 0 0 0 0 0dmoddreg1 0 0level0 1n1 0data
PTESTW DFC,<ea>,#<level>Test a Logical Address---3--1 1 1 1 0 0 0 0 0 0dmoddreg1 0 0level0 0 0 0 0 0 0 0 0 1
PTESTW DFC,<ea>,#<level>,AnTest a Logical Address---3--1 1 1 1 0 0 0 0 0 0dmoddreg1 0 0level0 1n0 0 0 0 1
PTESTW Dn,<ea>,#<level>Test a Logical Address---3--1 1 1 1 0 0 0 0 0 0dmoddreg1 0 0level0 0 0 0 0 0 1n
PTESTW Dn,<ea>,#<level>,AmTest a Logical Address---3--1 1 1 1 0 0 0 0 0 0dmoddreg1 0 0level0 1m0 1n
PTESTW SFC,<ea>,#<level>Test a Logical Address---3--1 1 1 1 0 0 0 0 0 0dmoddreg1 0 0level0 0 0 0 0 0 0 0 0 0
PTESTW SFC,<ea>,#<level>,AnTest a Logical Address---3--1 1 1 1 0 0 0 0 0 0dmoddreg1 0 0level0 1n0 0 0 0 0
PTESTW #<data>,<ea>,#<level>Test a Logical Address--M---1 1 1 1 0 0 0 0 0 0dmoddreg1 0 0level0 0 0 0 0 1d
PTESTW #<data>,<ea>,#<level>,AnTest a Logical Address--M---1 1 1 1 0 0 0 0 0 0dmoddreg1 0 0level0 1n 1d
PTESTW DFC,<ea>,#<level>Test a Logical Address--M---1 1 1 1 0 0 0 0 0 0dmoddreg1 0 0level0 0 0 0 0 0 0 0 0 1
PTESTW DFC,<ea>,#<level>,AnTest a Logical Address--M---1 1 1 1 0 0 0 0 0 0dmoddreg1 0 0level0 1n0 0 0 0 1
PTESTW Dn,<ea>,#<level>Test a Logical Address--M---1 1 1 1 0 0 0 0 0 0dmoddreg1 0 0level0 0 0 0 0 0 1n
PTESTW Dn,<ea>,#<level>,AmTest a Logical Address--M---1 1 1 1 0 0 0 0 0 0dmoddreg1 0 0level0 1m0 1n
PTESTW SFC,<ea>,#<level>Test a Logical Address--M---1 1 1 1 0 0 0 0 0 0dmoddreg1 0 0level0 0 0 0 0 0 0 0 0 0
PTESTW SFC,<ea>,#<level>,AnTest a Logical Address--M---1 1 1 1 0 0 0 0 0 0dmoddreg1 0 0level0 1n0 0 0 0 0
PTRAPccTRAP on PMMU Condition--M---1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 00 0 0 0 0 0 0 0 0 0 0pcc
PTRAPcc.L #<data>TRAP on PMMU Condition--M---1 1 1 1 0 0 0 0 0 1 1 1 1 0 1 10 0 0 0 0 0 0 0 0 0 0pcc
PTRAPcc.W #<data>TRAP on PMMU Condition--M---1 1 1 1 0 0 0 0 0 1 1 1 1 0 1 00 0 0 0 0 0 0 0 0 0 0pcc
PVALID.L An,<ea>Validate a Pointer--M---1 1 1 1 0 0 0 0 0 0dmoddreg0 0 1 0 1 1 0 0 0 0 0 0 0n
PVALID.L VAL,<ea>Validate a Pointer--M---1 1 1 1 0 0 0 0 0 0dmoddreg0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0
RESETThen Assert RESET (RSTO, MC68040 Only) Line0123460 1 0 0 1 1 1 0 0 1 1 1 0 0 0 0
ROL.sz #<data>,Dr左ローテート0123461 1 1 0data 1sz0 1 1dreg
ROL.sz Dq,Dr0123461 1 1 0sreg 1sz1 1 1dreg
ROL.sz Dr0123461 1 1 0 0 0 1 1sz0 1 1dreg
ROL.W <ea>0123461 1 1 0 0 1 1 1 1 1dmoddreg
ROR.sz #<data>,Dr右ローテート0123461 1 1 0data 0sz0 1 1dreg
ROR.sz Dq,Dr0123461 1 1 0sreg 0sz1 1 1dreg
ROR.sz Dr0123461 1 1 0 0 0 1 0sz0 1 1dreg
ROR.W <ea>0123461 1 1 0 0 1 1 0 1 1dmoddreg
ROXL.sz #<data>,DrXを含む左ローテート0123461 1 1 0data 1sz0 1 0dreg
ROXL.sz Dq,Dr0123461 1 1 0sreg 1sz1 1 0dreg
ROXL.sz Dr0123461 1 1 0 0 0 1 1sz0 1 0dreg
ROXL.W <ea>0123461 1 1 0 0 1 0 1 1 1dmoddreg
ROXR.sz #<data>,DrXを含む右ローテート0123461 1 1 0data 0sz0 1 0dreg
ROXR.sz Dr0123461 1 1 0 0 0 1 0sz0 1 0dreg
ROXR.sz Dq,Dr0123461 1 1 0sreg0 0 1 1 1 0dreg
ROXR.W <ea>0123461 1 1 0 0 1 0 0 1 1dmoddreg
RTD #<data>(SP)→PC,SP+4+d→SP-123460 1 0 0 1 1 1 0 0 1 1 1 0 1 0 0
RTE例外・割込から復帰0123460 1 0 0 1 1 1 0 0 1 1 1 0 0 1 1
RTM Rnモジュールからのリターン--2---0 0 0 0 0 1 1 0 1 1 0 0d
RTR(SP)→CCR,SP+2→SP,(SP)→PC,SP+4→SP0123460 1 0 0 1 1 1 0 0 1 1 1 0 1 1 1
RTS(SP)→PC,SP+4→SP0123460 1 0 0 1 1 1 0 0 1 1 1 0 1 0 1
SBCD.B -(Ar),-(Aq)-(Aq)- -(Ar)-X→(Aq) BCD0123461 0 0 0dreg1 0 0 0 0 1sreg
SBCD.B Dr,DqDq-Dr-X→Dq BCD0123461 0 0 0dreg1 0 0 0 0 0sreg
SCC.B <ea>cc ? 1 : 00123460 1 0 1cc1 1dmoddreg
STOP #<data>Load Status Register and Stop0123460 1 0 0 1 1 1 0 0 1 1 1 0 0 1 0
SUB.sz #<data>,<ea><ea>-#<data>→<ea>0123460 0 0 0 0 1 0 0szdmoddreg
SUB.sz <ea>,DqDq-<ea>→Dq0123461 0 0 1dreg 0szdmoddreg
SUB.W <ea>,AqAq-<ea>→Aq0123461 0 0 1dreg0 1 1smodsreg
SUB.L <ea>,AqAq-<ea>→Aq0123461 0 0 1dreg1 1 1smodsreg
SUB.sz Dq,<ea><ea>-Dq→<ea>0123461 0 0 1sreg 1szdmoddreg
SUBQ.sz #<data>,<ea><ea>-#<data>→<ea>0123460 1 0 1sreg 1szdmoddreg
SUBQ.L #<data>,ArAr-#<data>→Ar0123460 1 0 1data1 1 0 0 0 1dreg
SUBQ.W #<data>,ArAr-#<data>→Ar0123460 1 0 1data1 0 1 0 0 1dreg
SUBX.sz -(Ar),-(Aq)-(Aq)- -(Ar)-X→(Aq)0123461 0 0 1dreg 1sz0 0 1sreg
SUBX.sz Dr,DqDq-Dr-X→Dq0123461 0 0 1dreg 1sz0 0 0sreg
SWAP.W DrDn(31～16bit)⇄Dn(15～0)0123460 1 0 0 1 0 0 0 0 1 0 0 0dreg
TAS.B <ea>Destination Tested→Condition Codes; 1→ Bit 7 of Destination0123460 1 0 0 1 0 1 0 1 1dmoddreg
TPcc.Sz/TRAPcc.Szif cc then trap--23460 1 0 1cc1 1 1 1 1Sz
TST.sz <ea><ea>→cc0123460 1 0 0 1 0 1 0Szdmoddreg
UNLK ArAn→SP (SP)→An Sp+4→SP0123460 1 0 0 1 1 1 0 0 1 0 1 1dreg
UNPK -(Ar),-(Aq),#<data>Unpack BCD--23461 0 0 0dreg1 1 0 0 0 1sreg
UNPK Dr,Dq,#<data>Unpack BCD--23461 0 0 0dreg1 1 0 0 0 0sreg
SZ Field Encode
codeoperation
01Byte
10Long
11Word
sz Field Encode
codeoperation
00Byte
01Word
10Long
Sz Field Encode
codeoperation
010Word
011Long
100none
sZ Field Encode
codeoperation
00Byte
10Word
11Long
FSZ Field Encode
code符号データー型
000L32bit整数
001S単精度浮動小数点
010X拡張倍精度浮動小数点
011PPacked Decimal Real
100W16bit整数
101D倍精度浮動小数点
111B8bit整数
cache Field Encode
code略説明
00NCNo Operation
01DCData Cache
10ICInstruction Cache
11BCData & Instruction Cache
scope Field Encode
code略説明
00Illegal
01LLine
10PPage
11AAll
reg Field Encode
codedataadsFPU
000D0A0FP0
001D1A1FP1
010D2A2FP2
011D3A3FP3
100D4A4FP4
101D5A5FP5
110D6A6FP6
111D7A7FP7
mod Field Encode
modregaddressing
000nDn
001nAn
010n(An)
011n(An)+
100n-(An)
101n(d16,An)
110n(d8,An,Xi)
111000(xxx).W
111001(xxx).L
111010(d16,PC)
111011(d8,PC,Xi)
111100#<data>
ブリーフフォーマット拡張ワード(MPU=012346)
1514131211109876543210
daregWLsc0d
ブリーフフォーマット拡張ワード(MPU=--2346)
1514131211109876543210
daregWLsc1BSISBD Size0I/IS
WL
0Word 符号拡張
1Long Word
Scale(SC)
codescaleMPU
00*1012346
01*2--2346
10*4--2346
11*8--2346
ベースレジスタサプレス(BS)
codescale
0ベースレジスタを加える
1ベースレジスタを省略
インデックスサプレス(IS)
codescale
0インデックスオペランドを評価
1インデックスオペランドを省略
ベースディスプレースメントサイズ(BD SIZE)
codescale
00予約
01ベースディスプレースメントなし
10ワードディスプレースメント
11ロングワードディスプレースメント
インデックスおよび間接選択(I/IS)
codescale
IS I/IS 文法
0 000 (bd,An,Xi)
0 001 ([bd,An,Xi])
0 010 ([bd,An,Xi],od.W)
0 011 ([bd,An,Xi],od.L)
0 100
0 101 ([bd,An],Xi)
0 110 ([bd,An],Xi,od.W)
0 111 ([bd,An],Xi,od.L)
1 000 (bd,An)
1 001 ([bd,An])
1 010 ([bd,An],od.W)
1 011 ([bd,An],od.L)
1 100-111
CONTROL REGISTER NUMBER FIELD
NumberRegMPU
000000000000SFC-12346
000000000001DFC-12346
000000000010CACR--2346
000000000011TC----46
000000000100ITT0----46
000000000101ITT1----46
000000000110DTT0----46
000000000111DTT1----46
000000001000BUSCR-----6
100000000000USP-12346
100000000001VBR-12346
100000000010CAAR--23--
100000000011MSP--234-
100000000100ISP--234-
100000000101MMUSR----4-
100000000110URP----46
100000000111SRP----46
100000001000PCR-----6
Offset Constant
00π
0BLog10(2)
0Ce
0DLog2(e)
0ELog10(e)
0F0.0
301n(2)
311n(10)
32100
33101
34102
35104
36108
371016
381032
391064
3A10128
3B10256
3C10512
3D101024
3E102048
3F104096
Specifier Description Condition Field
codeSpecifierDescriptioncodeSpecifierDescription
000000BSB set000001BCB clear
000010LSL set000011LCL clear
000100SSS set000101SCS clear
000110ASA set000111ACA clear
001000WSW set001001WCW clear
001010ISI set001011ICI clear
001100GSG set001101GCG clear
001110CSC set001111CCC clear
DA Field
0data register
1address register
Condition Code
code二モニックboolean説明
0000RA1always true
00010always false
0010HI,NLS~C&~Zhigh
0011LS,NHIC|Zlow or same
0100CC,HS,NCS~Ccarry clear (high or same)
0101CS,LO,NCC,NHSCcarry set (low)
0110NE,NEQ,NZ,NZE~Znot equal
0111EQ,NNE,ZEZequal
1000VC,NVS~Voverflow clear
1001VS,NVCVoverflow set
1010PL,NMI~Nplus
1011MI,NPLNminus
1100GE,GLTN&V|~N&~Vgreater or equal
1101LT,NGEN&~V|~N&Vless than
1110GT,NLEN&V&~Z|~N&~V&~Zgreater than
1111LE,NGTZ|N&~V|~N&Vless or equal
FPU Condition Code
code二モニック説明
000000FFalse
000001EQEqual
000010OGTOrdered Greater Than
000011OGEOrdered Greater Than or Equal
000100OLTOrdered Less Than
000101OLEOrdered Less Than or Equal
000110OGLOrdered Greater Than or Less Than
000111OROrdered
001000UNUnordered
001001UEQUnordered or Equal
001010UGTUnordered or Greater Than
001011UGEUnordered or Greater Than or Equal
001100ULTUnordered or Less Than
001101ULEUnordered or Less Than or Equal
001110NENot Equal
001111TAlways True
010000SFSignaling Always False
010001SEQSignaling Equal
010010GTGreater Than
010011GEGreater Than or Equal
010100LTLess Than
010101LELess Than or Equal
010110GLGreater Than or Less Than
010111GLEGreater Than or Less Than or Equal
011000NGLENot (greater than or less than or equal)
011001NGLNot (greater than or less than)
011010NLENot (less than or equal)
011011NLTNot Less Than
011100NGENot (greater than or equal)
011101NGTNot Greater Than
011110SNESignaling Not Equal
011111STSignaling Always True
register list(not predecrement)
1514131211109876543210
A7A6A5A4A3A2A1A0D7D6D5D4D3D2D1D0
register list(predecrement)
1514131211109876543210
D0D1D2D3D4D5D6D7A0A1A2A3A4A5A6A7
floating-point register list(not predecrement)
76543210
FP7FP6FP5FP4FP3FP2FP1FP0
floating-point register list(predecrement)
76543210
FP0FP1FP2FP3FP4FP5FP6FP7
Register List field
Bit NumberRegister
12Flosting-Point Control Register
11Floating-Point Status Register
10Floating-Point Instruction Address Register
Register List field
MREGSizeRegisterMPU
000LongTranslation Control RegsiterM3
001QurdDMA Root Pointer
010QurdSupervisor Root PointerM3
011QurdCPU Root PointerM3
100QurdCurrent Access Level
101ByteValid Access Level
110ByteStack Change Control Regsiter
111WordAccess Control Regsiter
≠ 等しくない
∨Boolean OR
⊻Boolean exclusive OR
∧ Boolean AND
￢ Boolean Not
% 余
>> 右シフト
<< 左シフト
⇄ 交換
== イコール
&& and